Regd-Rule 12.6 and 12.7

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Nasi
Posts: 1
Joined: Wed Jan 21, 2015 11:28 am
Company: HyundaiMobis

Regd-Rule 12.6 and 12.7

Post by Nasi » Fri Jan 23, 2015 3:54 am

The following code is Auto generated code from Embedded Coder of Matlab Simulink.

Code: Select all

tmp = Common_Signal_Process_DWork.UnitDelay_DSTATE_b[1] * ((int16_T)(16384 -
      Common_Signal_Process_DWork.UnitDelay3_DSTATE_d));

    /* Switch: '<S68>/Thrs~=4' incorporates:
     *  Product: '<S68>/Product1'
     *  Switch: '<S68>/Thrs~=3'
     */
    rtb_Thrs5_idx_1 = (int16_T)((tmp >> 14) + ((tmp & 8192) != 0));
    rtb_Thrs5_idx_2 = Common_Signal_Process_DWork.UnitDelay_DSTATE_b[2];
    rtb_Thrs5_idx_3 = Common_Signal_Process_DWork.UnitDelay_DSTATE_b[3];
  } 

rtb_Thrs5_idx_1 = (int16_T)((tmp >> 14) + ((tmp & 8192) != 0));
On the Highlighted code above, we are getting MISRA-C 12.6 and 12.7 Rule violations. How to remove this violation?

misra-c
Posts: 569
Joined: Thu Jan 05, 2006 1:11 pm

Re: Regd-Rule 12.6 and 12.7

Post by misra-c » Fri Feb 13, 2015 9:49 am

Given the cast on the first line, we assume that "tmp" has a "signed short" or "signed int" type. "tmp & 8192" therefore violates rule 12.7.

The result of "((tmp & 8192) != 0)" is effectively Boolean and is used as an operand to "+", which therefore violates rule 12.6.

The MISRA-C Working Group can make no further comment as to how a particular auto-coder can be configured to avoid these violations, but perhaps other users may help you.
---
Posted by and on behalf of
the MISRA C Working Group

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